to describe configurable components using metadata, and.to enable exchanging complex component libraries between electronic design automation (EDA) tools for SoC design (design environments),.to ensure delivery of compatible component descriptions from multiple component vendors,.IP-XACT was created by the SPIRIT Consortium as a standard to enable automated configuration and integration through tools.
IP-XACT is an XML format that defines and describes individual, re-usable electronic circuit designs (individual pieces of intellectual property, or IPs) to facilitate their use in creating integrated circuits (i.e. ( January 2019) ( Learn how and when to remove this template message) Please help to improve this article by introducing more precise citations. From the results, we can see that the defined IP-XACT mutation serves an effective qualification for simulation tests, in terms of its ability to reveal the weakness of the tests.This article includes a list of general references, but it lacks sufficient corresponding inline citations. Then several experiments were conducted on a TLM library for CoreConnect SoC modeling. We implemented the code generator and mutation operators in an Eclipsed-based IP-XACT editor with the help of Eclipse Modeling Framework. With IP-XACT, the mutation maintains a focus on the integration and configuration of components. Second, we define the mutation operators on IP-XACT schema, which is the model of errors that we can inject into IP-XACT designs during mutation testing.
For this, we created a code generator that generates SystemC models from IP-XACT XML designs, such that we can simulate and test an IP-XACT design. First, as IP-XACT system designs are XML files, which are not originally for execution, we need an execution/simulation engine for IP-XACT designs. Two major ingredients are required for this extension. In this paper, we present our effort to enable the mutation-based simulation coverage metric for system level IP integration with IP-XACT. On the other hand, IP-XACT has evolved to the IEEE standard for IP reuse and IP-based System-on-Chip (SoC) integration, which covers both RTL and TLM. Mutation-testing has been considered as an important coverage metric to measure the quality of simulation-based verification and validation processes.
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